The present invention is directed to a system for testing memory devices.
It is well known to use a test system to test the reliability of a semiconductor device, such as a conventional dynamic random access memory (DRAM) or static random access memory (SRAM). The conventional test system typically provides a test signal pattern (so called xe2x80x9ctest vectorxe2x80x9d) to a semiconductor device under test (xe2x80x9cDUTxe2x80x9d) and compares an output signal from the DUT with an expected signal to determine whether the DUT functions correctly. For exemplary test systems, see, for example, U.S. Pat. No. 5,946,247 to Osawa et al.; U.S. Pat. No. 4,862,460 to Yamaguchi; and U.S. Pat. No. 4,502,127 to Garcia et al, which are incorporated herein by reference in their entirety.
Recently introduced memory devices, such as Direct RDRAM(trademark) from RAMBUS of Mountain View, Calif., use variably time spaced, xe2x80x9cpacketxe2x80x9d based address and data communications. A xe2x80x9cpacketxe2x80x9d includes multiple xe2x80x9cstreamsxe2x80x9d transmitted in parallel, where each stream is 8 serial ordered bits. For a description of Direct RDRAM(trademark), see the Direct RDRAM(trademark) Datasheet available from RAMBUS, which is incorporated by reference herein in its entirety. Herein, xe2x80x9cDirect RDRAM(trademark)xe2x80x9d means any device compatible with the Direct RDRAM(trademark) such as Synclink. Such address and data packet communications further include interspersed instructions. Thus, to test such recent memory systems, a test system must provide such variably time spaced and instruction-interspersed, packet based communications.
FIG. 1A depicts in a block diagram form a Direct RDRAM(trademark) device 100. Direct RDRAM(trademark) device 100 includes distinct terminals labeled ROW, COLUMN, DATA0, and DATAl. Commands xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d are input to terminal ROW. Commands xe2x80x9cCOLC/Mxe2x80x9d and xe2x80x9cCOLC/Xxe2x80x9d are input to terminal COLUMN. Commands xe2x80x9cDQAxe2x80x9d and xe2x80x9cDQBxe2x80x9d are input to respective terminals DATA0 and DATA1. Direct RDRAM(trademark) uses the packet-based commands xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d for row identification, xe2x80x9cCOLC/Mxe2x80x9d and xe2x80x9cCOLC/Xxe2x80x9d for column identification, and a combination of. xe2x80x9cDQAxe2x80x9d and xe2x80x9cDQBxe2x80x9d for data specification.
FIG. 1B depicts the bit designations of commands xe2x80x9cROWAxe2x80x9d, xe2x80x9cROWRxe2x80x9d, xe2x80x9cCOLCxe2x80x9d, xe2x80x9cCOLXxe2x80x9d and xe2x80x9cCOLMxe2x80x9d. Command xe2x80x9cCOLC/Xxe2x80x9d is a combination of commands xe2x80x9cCOLCxe2x80x9d and xe2x80x9cCOLXxe2x80x9d whereas xe2x80x9cCOLC/Mxe2x80x9d is a combination of commands xe2x80x9cCOLC xe2x80x9d and xe2x80x9cCOLMxe2x80x9d. Commands xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d each include three streams (numbered 0 to 2), each stream being 8 bits in serial order. As shown, command xe2x80x9cROWAxe2x80x9d includes bits xe2x80x9cDR4Txe2x80x9d, xe2x80x9cDR4Fxe2x80x9d, xe2x80x9cDR0xe2x80x9d to xe2x80x9cDR3xe2x80x9d, xe2x80x9cBR0xe2x80x9d to xe2x80x9cBR3xe2x80x9d, 2 bits of xe2x80x9cRsvBxe2x80x9d, 2 bits of xe2x80x9cRsvRxe2x80x9d, xe2x80x9cAVxe2x80x9d, and xe2x80x9cR0xe2x80x9d to xe2x80x9cR8xe2x80x9d. Direct RDRAM(trademark) defines xe2x80x9cDR4Txe2x80x9d and xe2x80x9cDR4Fxe2x80x9d as bits for framing (recognizing) a xe2x80x9cROWAxe2x80x9d or xe2x80x9cROWRxe2x80x9d command; xe2x80x9cDR0xe2x80x9d to xe2x80x9cDR3xe2x80x9d, xe2x80x9cDR4Txe2x80x9d, and xe2x80x9cDR4Fxe2x80x9d as a device address for xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d commands; xe2x80x9cBR0xe2x80x9d to xe2x80x9cBR3xe2x80x9d as a bank address for xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d commands; xe2x80x9cAVxe2x80x9d as a bit for selecting between xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d commands; and xe2x80x9cR0xe2x80x9d to xe2x80x9cR8xe2x80x9d as a row address for the xe2x80x9cROWAxe2x80x9d and xe2x80x9cROWRxe2x80x9d commands. The two bits of xe2x80x9cRsvBxe2x80x9d are reserved for future bank address extensions whereas the two bits of xe2x80x9cRsvRxe2x80x9d are reserved for future row address extensions.
Command xe2x80x9cROWRxe2x80x9d is used to precharge address specified memory cells, which will be accessed subsequently. The bit designations of command xe2x80x9cROWRxe2x80x9d are the same as those of command xe2x80x9cROWAxe2x80x9d except bit AV is 0.
As shown in FIG. 1B, command xe2x80x9cCOLCxe2x80x9d includes bits xe2x80x9cSxe2x80x9d, xe2x80x9cDC0xe2x80x9d to xe2x80x9cDC4xe2x80x9d, xe2x80x9cC0xe2x80x9d to xe2x80x9cC5xe2x80x9d, xe2x80x9cRsvCxe2x80x9d, xe2x80x9cBC0xe2x80x9d to xe2x80x9cBC3xe2x80x9d, 2 bits of xe2x80x9cRsvBxe2x80x9d, and xe2x80x9cCOP0xe2x80x9d to xe2x80x9cCOP3xe2x80x9d. Direct RDRAM(trademark) defines xe2x80x9cSxe2x80x9d as a bit for framing (recognizing) the xe2x80x9cCOLCxe2x80x9d command; xe2x80x9cDC0xe2x80x9d to xe2x80x9cDC4xe2x80x9d as a device address for the xe2x80x9cCOLCxe2x80x9d command; xe2x80x9cC0xe2x80x9d to xe2x80x9cC5xe2x80x9d as a column address for the xe2x80x9cCOLCxe2x80x9d command; xe2x80x9cRsvCxe2x80x9d as a bit reserved for future expansion of the column address; xe2x80x9cBCOxe2x80x9d to xe2x80x9cBC3xe2x80x9d as a bank address for the xe2x80x9cCOLCxe2x80x9d command; 2 bits of xe2x80x9cRsvBxe2x80x9d as bits reserved for future expansion of the bank address; and xe2x80x9cCOPOxe2x80x9d to xe2x80x9cCOP3xe2x80x9d as used to specify read, write, precharge, and power management functions.
As shown in FIG. 1B, command xe2x80x9cCOLCxe2x80x9d includes undefined bits, shown as asterisk. Commands xe2x80x9cCOLXxe2x80x9d and xe2x80x9cCOLMxe2x80x9d are inserted into the undefined bits of command xe2x80x9cCOLCxe2x80x9d to form respective commands xe2x80x9cCOLC/Xxe2x80x9d and xe2x80x9cCOLC/Mxe2x80x9d. Commands xe2x80x9cCOLC/Xxe2x80x9d and xe2x80x9cCOLC/Mxe2x80x9d each include five streams (numbered 0 to 4), each being 8 bits in serial order.
Command xe2x80x9cCOLC/Xxe2x80x9d is used to specify an independent precharge command and for housekeeping and power management. Command xe2x80x9cCOLC/Xxe2x80x9d includes bits xe2x80x9cMxe2x80x9d, xe2x80x9cDX0xe2x80x9d to xe2x80x9cDX4xe2x80x9d, xe2x80x9cXOP0xe2x80x9d to xe2x80x9cXOP4xe2x80x9d, xe2x80x9cBX0xe2x80x9d to xe2x80x9cBX3xe2x80x9d, and 2 xe2x80x9cRsvBxe2x80x9d bits. Direct RDRAM(trademark) defines xe2x80x9cM=0xe2x80x9d as identifying the xe2x80x9cCOLC/Xxe2x80x9d command; xe2x80x9cDX0xe2x80x9d to xe2x80x9cDX4xe2x80x9d as specifying the device address for the xe2x80x9cCOLC/Xxe2x80x9d command; xe2x80x9cXOP0xe2x80x9d to xe2x80x9cXOP4xe2x80x9d as an opcode field for the xe2x80x9cCOLC/Xxe2x80x9d command to specify precharge and power management functions; xe2x80x9cBX0xe2x80x9d to xe2x80x9cBX3xe2x80x9d as a bank address for the xe2x80x9cCOLC/Xxe2x80x9d command; and the 2 xe2x80x9cRsvBxe2x80x9d bits as reserved for expansion of the bank address.
Command xe2x80x9cCOLC/Mxe2x80x9d is used to specify byte mask control. Command xe2x80x9cCOLC/Mxe2x80x9d includes bits xe2x80x9cMxe2x80x9d, xe2x80x9cMA0xe2x80x9d to xe2x80x9cMA7 xe2x80x9d, and xe2x80x9cMB0xe2x80x9d to xe2x80x9cMB7xe2x80x9d. Direct RDRAM(trademark) defines xe2x80x9cM=1xe2x80x9d as identifying the xe2x80x9cCOLC/Mxe2x80x9d command; xe2x80x9cMA0xe2x80x9d to xe2x80x9cMA7xe2x80x9d as byte mask write control bits; and xe2x80x9cMB0xe2x80x9d to xe2x80x9cMB7xe2x80x9d as byte mask write control bits.
Direct RDRAM(trademark) defines data commands xe2x80x9cDQAxe2x80x9d and xe2x80x9cDQBxe2x80x9d each as nine streams (numbered 0 to 8), each stream including 8 bits in serial order. Commands xe2x80x9cDQAxe2x80x9d and xe2x80x9cDQBxe2x80x9d include only data.
FIG. 1C schematically depicts an exemplary sequence of packet-based commands xe2x80x9cROWAxe2x80x9d, xe2x80x9cROWRxe2x80x9d, xe2x80x9cCOLC/Mxe2x80x9d, xe2x80x9cCOLC/Xxe2x80x9d, xe2x80x9cDQAxe2x80x9d, and xe2x80x9cDQBxe2x80x9d. The time spacing between the start and ending of sequential, packet-based commands is variable.
One conventional test system uses multiple accelerated APGs (algorithmic pattern generators) to generate address and data commands at a rate required by a Direct RDRAM(trademark) compatible DUT. For descriptions of exemplary APGs, see U.S. Pat. No. 5,946,247 to Osawa et al.; U.S. Pat. No. 4,862,460 to Yamaguchi; and U.S. Pat. No. 4,502,127 to Garcia et al, which are incorporated by reference herein in their entirety. However, such accelerated APGs are expensive. Further, complex logic circuitry is required to form commands from the address and data from the multiple APGs thereby making the test system difficult for a tester to use.
Thus what is needed is a test system that provides variably time spaced, packet based communications to test DUTs without use of multiple accelerated APGs.
An embodiment of the present invention includes a packet generator that generates packet-based address and data commands to a device under test (DUT). In one embodiment, the packet generator receives column and row addresses and data from a single conventional (non-accelerated) algorithmic pattern generator (APG) and generates column and row addresses and data in packet form, thereby allowing communications with a packet-based device, such as a memory system. The packet generator further provides variable time spacing between column and row addresses and data packets without modification of a conventional timing and formatting circuitry. Thereby, the packet generator advantageously allows testing of memory DUTs that require signal inputs at a higher rate than a conventional APG can provide.
Thereby an embodiment of the present invention includes a method of providing packet-based address and data commands to a device under test (DUT), the method including the acts of: providing a data at a data rate; providing addresses at an address rate; providing user-specified instructions; providing to the DUT address packets that include the addresses and the user-specified instructions at a rate faster than the address rate; and providing to the DUT data packets that include the data and the user-specified instructions at a rate faster than the data rate.